The present invention relates to the manufacturing of semiconductor devices, and more particularly, to forming measurement structures that include embedded transistors.
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a metal-oxide-semiconductor(MOS) transistor. The MOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the MOS transistor is increased and as manufacturing costs are reduced.
A typical MOS device includes a bulk semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, receives an input signal to control operation of the device. Source and drain regions are typically formed in regions of the substrate adjacent the gate electrodes by doping the regions with a dopant of a desired conductivity. The conductivity of the doped region depends on the type of impurity used to dope the region. The typical MOS device is symmetrical, in that the source and drain are interchangeable. Whether a region acts as a source or drain typically depends on the respective applied voltages and the type of device being made. The collective term source/drain region is used herein to generally describe an active region used for the formation of either a source or drain.
During the manufacturing process, a semiconductor device undergoes many types of metrology to ensure the quality of the semiconductor device. For example, processes, such as lithography, are controlled, in part, by taking dimensional measurements of certain features of the semiconductor device formed by the lithography process. One type of measurement technique used to measure the dimensions of a structure in a semiconductor device is scatterometry. Scatterometry is a non-destructive optical technique that records and analyzes changes in the intensity of light reflected from a periodic scattering surface. By measuring and analyzing the light diffracted from a patterned periodic sample, the dimensions of the sample structure can be measured.
A structure commonly known as a grate is used typically used with scatterometry to determine dimensions, such as gate electrode width, in a semiconductor device. The grate is comprised of several parallel lines that are formed in the same manner as the gate electrodes of the semiconductor device. The grate, however, serves no other purpose. Because of the ever increasing need to fit more transistors into a semiconductor device, there is a desire to improve the utilization of all available space in a given semiconductor device. Furthermore, there is a recognized desire to be able to compare the measured line width of a gate electrode of a functional transistor to other electrical characteristics of the transistor. Accordingly, a need exists for an improved semiconductor device and method of forming the same that allows for improved space utilization and the ability to compare different electrical characteristic performance of a transistor.
This and other needs are met by embodiments of the present invention which provide a semiconductor device in which the same structure can be used for inline metrology of the semiconductor device and also serve as a gate electrode line of a transistor. The semiconductor device includes a grating structure having a plurality of parallel lines, and at least one of the parallel lines is a gate electrode line of a transistor, which includes source/drain regions proximate to the gate electrode line, and vias extending to the gate electrode line and the source/drain regions.
In another aspect of the present invention, the lines are formed from polysilicon. Also, the gate electrode line is positioned at a center of the grating structure, as viewed from above, and the gate electrode line has a greater length than other lines in the grating structure.
In another embodiment of the present invention, a method of manufacturing a semiconductor device is provided. The method includes depositing a layer over a substrate; and etching the layer to form a grating structure. The grating structure includes a plurality of parallel lines and at least one of the multiple parallel lines is a gate electrode line of a transistor. The method also includes the steps of forming an insulator layer prior to depositing the layer, forming source/drain regions proximate to the gate electrode line, and forming vias to the source/drain regions and to the gate electrode line.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.